SAN JOSE, CA, Sep 23, 2026 – Cadence’s new RTL Generation Agent automates digital design creation, analysis and refinement through natural language prompts. Part of ChipStack AI Super Agent, it converts specifications into register-transfer-level code optimized for power, performance and area.
The agent extends ChipStack’s verification and debugging capabilities into RTL generation and optimization. Cadence introduced the front-end design and verification workflow in February 2026.
In early evaluations, Cadence reported average area reductions of 24% and power reductions of 18% against foundation-model-only code generation. The company also reported 100% functional accuracy for the RTL generated in those evaluations.
“These latest agentic AI advancements take us from AI‑assisted tools to coordinated agentic workflows that behave more like virtual design engineers with expert-level command of the underlying technologies,” said Chin-Chi Teng, senior vice president and general manager in the digital & signoff group, Cadence. “By pairing agentic automation of spec-to-RTL and RTL refinement with our proven implementation and signoff engines, we enable customers to achieve better design outcomes with higher productivity and stronger correlation across the design flow, further extending Cadence’s leadership in AI‑driven, end‑to‑end chip design.”
Cadence’s super agents coordinate task-specific agents that use electronic design automation software adapted for agent workflows. This structure connects design automation with the company’s implementation and signoff tools.
Honda Evaluates Automotive Designs
Honda R&D is evaluating the RTL Generation Agent for automotive systems-on-chip (SoC) with safety requirements and power and cost constraints. Its work focuses on productivity from specification through RTL development.
“As a key enabler of Software-Defined Vehicles (SDVs), AI technology for autonomous driving is advancing rapidly. However, the long development cycle of SoCs remains a major challenge. With the Cadence ChipStack AI Super Agent’s RTL Generation Agent and AI-powered automation, Honda R&D is working to improve productivity from specification through RTL development,” said Tomoya Nishino, chief engineer and general manager, digital engine development division, SDV R&D center, Honda R&D Co., Ltd.
Updates to Existing RTL
Cadence is also introducing an automated workflow for adapting existing RTL to new requirements. Engineers describe changes to architecture, power, performance, area or functionality at a high level. Agents then revise the code while analyzing and verifying those design characteristics.
The developments follow Cadence’s June announcement of an autonomous virtual engineer for chip design. Its ChipStack, InnoStack and ViraStack AI Super Agent portfolio covers digital design, analog design and verification.
Cadence expects the expanded ChipStack and InnoStack capabilities to become available to select customers in Q4, 2026.
Source: Cadence
About Cadence
Cadence Design Systems is a U.S.-based technology firm that develops electronic design automation (EDA) tools, hardware, and IP for designing integrated circuits and electronic systems. Formed in 1988 through the merger of SDA Systems and ECAD, the company is headquartered in San Jose, CA. Cadence provides software and solutions for designing SoCs, PCBs, and complete electronic systems used in the semiconductor, automotive, aerospace and defense, telecommunications, and consumer electronics industries. Its tools support both digital and analog design workflows. Cadence employs about 12,000 people globally.
