OpenAI has demonstrated how large language models (LLMs) can accelerate semiconductor development through Jalapeño, its first custom AI accelerator. The chip progressed from initial architecture to first silicon in less than 20 months, with just 9 months between register-transfer level (RTL) development and tape-out, tells IEEE Spectrum.
Jalapeño delivers up to 13.4 petaflops of 4-bit computing performance, supported by 232 gigabytes of HBM4 memory and 15.4 terabytes per second of memory bandwidth. OpenAI reports that it can reduce end-to-end inference latency by up to 3.6 times compared with Nvidia’s GB300 while consuming less power.
The project involved an OpenAI hardware team averaging fewer than 100 people, alongside semiconductor partner Broadcom. OpenAI handled system architecture, memory hierarchy, networking, and accelerator design, while Broadcom managed physical implementation and manufacturing preparation.
A key innovation was integrating LLMs with Accelerated Hardware Synthesis (XLS), an open-source framework originally developed at Google. Engineers used programming languages such as C++ and DSLX to describe hardware behavior, which XLS translated into Verilog. This approach allowed AI models to work within familiar software environments and accelerate design iterations.
AI also improved software optimization. On a DeepSeek attention-kernel benchmark, performance increased from 0.31% to 88.94% of the chip’s theoretical ceiling in approximately 40 hours.
Physical design showed additional benefits. AI-guided optimization reduced the area occupied by matrix multiplication units by 10% compared with an optimized human baseline.
However, AI contributed more effectively to front-end development than backend tasks such as routing, timing, and power verification.
OpenAI plans to expand AI assistance into verification, waveform analysis, and physical design for subsequent chip generations.
The project illustrates a shift toward AI-assisted semiconductor engineering, where smaller teams can explore more design alternatives, accelerate development, and improve hardware performance without eliminating human expertise or engineering oversight.
