A team at King Abdullah University of Science and Technology (KAUST) has broken new ground in semiconductor design by achieving a six-layer stack of hybrid complementary metal-oxide semiconductor (CMOS) transistors for large-area electronics, tells Tech Xplore. This sets a new benchmark, since previous hybrid CMOS designs never exceeded two stacks. Their work appears in the journal Nature Electronics and signals a pathway beyond the limits of planar scaling.
Traditional scaling, squeezing more transistors on a flat plane, has run into physical and economic limits, especially as further shrinkage triggers quantum effects, heat issues, and skyrocketing costs. The KAUST team argues that stacking vertically is the next frontier. But stacking layers is difficult: new layers must not disturb the ones underneath, and alignment, heat, and roughness become harder to control. In their process, the team managed to keep all fabrication steps below 150°C (well lower than typical semiconductor processing) and maintained very smooth surfaces to ensure good alignment and connectivity between layers.
Their vertical design increases the density of functional circuits without expanding chip area. It also supports large-area electronics, such as flexible displays, wearable electronics, and sensors, where conventional rigid silicon chips are less suitable. By refining fabrication, layer alignment, and surface quality, they provide a blueprint for scaling up transistor stacking.
This milestone isn’t just about stacking more parts; it’s about enabling more powerful, energy-efficient electronics. If these techniques mature, future devices, wearables, and smart surfaces could carry complex logic and sensor networks embedded in flexible, thin substrates. The KAUST result shows that vertical integration is no longer hypothetical.