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Cadence Launches ChipStack AI Super Agent to Automate Chip Design

by | Feb 12, 2026

Automates front-end chip design and verification workflows, including testbench coding, test plans, regressions, debugging and fixes

SAN JOSE, CA, Feb 12, 2026 – Cadence launched the ChipStack AI Super Agent, an agentic AI workflow for front-end silicon design and verification. The tool automates key steps in chip design and verification, including coding designs and testbenches, creating test plans, running regression tests, debugging, and fixing issues.

“ChipStack represents a major leap in our design-for-AI and AI-for-design strategy, applying agentic AI directly to our customers’ front-end flows to tackle the growing complexity and scale of modern chips,” said Anirudh Devgan, president and CEO, Cadence. “By leveraging intelligent agents that autonomously call our underlying tools, we are enabling dramatic productivity gains for our customers in critical design and verification tasks while freeing scarce engineering talent to focus on innovation.”

Cadence is positioning the ChipStack AI Super Agent as a front-end workflow that coordinates multiple virtual engineers using its EDA tools. The company links it to its Intelligent System Design strategy, which combines AI orchestration, simulation, and accelerated computing. Cadence says the system builds on its optimization AI and AI assistant products used in more than 1,000 tapeouts. That lineup includes the Verisium verification platform, Cadence Cerebrus Intelligent Chip Explorer, and Cadence’s JedAI data and AI platform.

The ChipStack AI Super Agent supports frontier models in the cloud and on premises. Supported options include open NVIDIA Nemotron models, customizable with NVIDIA NeMo, and cloud-hosted models such as OpenAI GPT. Cadence calls it another step toward a “silicon agent” that spans the design disciplines and workflows behind next-generation intelligent devices.

“Our customers are facing a significant senior deficit in the engineering talent needed to deliver on their product roadmaps,” said Paul Cunningham, vice president and general manager of R&D, Cadence. “Our ChipStack AI Super Agent is a game changer for design and verification productivity, and deployments are ramping fast.”

“The Cadence ChipStack AI Super Agent has significantly reduced our verification effort in some areas by approximately 10X, enabling our team to achieve closure much more swiftly and confidently,” stated Arvind Vidyarthi, senior director of engineering, Altera. “By pairing an interactive, engineer-in-the-loop experience with Cadence’s advanced AI-driven verification technologies, we are realizing step-function productivity gains and achieving deeper functional coverage on our most complex designs.”​

“As semiconductor complexity continues to accelerate, AI has become essential to designing the next generation of chips,” said Timothy Costa, GM of industrial and computational engineering, NVIDIA. “Our collaboration with Cadence, including innovations like the ChipStack AI Super Agent, demonstrates how combining intelligent reasoning capabilities such as Mental Models and automated formal test plan generation with NVIDIA accelerated computing can unlock new levels of productivity and efficiency for chip designers.”

“Qualcomm is pleased to collaborate with Cadence on the evaluation of the ChipStack AI Super Agent for a broad user base,” said Paul Penzes, vice president of engineering at Qualcomm. “Early results indicate strong, encouraging performance enhancements, and we look forward to realizing the productivity gains.”

“ChipStack greatly improved the efficiency of our formal verification efforts,” said Daniel Cummings, principal engineer of RISC-V Cores, Tenstorrent. “During a three-month evaluation on three critical design blocks, it reduced verification time by up to 4X. Running the agent on Tenstorrent hardware also demonstrated our ability to deliver the high-performance, on-prem inference needed for production-scale LLM workloads.”

Source: Cadence

About Cadence

Cadence Design Systems, Inc. is a U.S.-based technology firm that develops electronic design automation (EDA) tools, hardware, and IP for designing integrated circuits and electronic systems. Formed in 1988 through the merger of SDA Systems and ECAD, the company is headquartered in San Jose, CA. Cadence provides software and solutions for designing SoCs, PCBs, and complete electronic systems used in the semiconductor, automotive, aerospace and defense, telecommunications, and consumer electronics industries. Its tools support both digital and analog design workflows. As of 2024, Cadence employed about 12,000 people globally. The company’s technology supports the design, verification, and optimization of complex electronics across various industries.