MIT engineers have developed a new fabrication approach that could significantly boost the energy efficiency of electronic devices by changing how components are stacked on a chip. Traditional microelectronics separate logic elements such as transistors from memory and other functional parts, forcing data to travel back and forth through long electrical paths. That movement wastes energy and limits performance. The new method instead stacks multiple active components directly on top of an existing circuit, reducing wasted energy and shortening data pathways, tells MIT News.
In conventional silicon chips, the “front end” houses transistors and computational elements, while the “back end” holds metal interconnects that link those parts together. Data moving across those interconnects dissipates power and limits speed. To address this, MIT researchers have developed an integration platform that lets them fabricate active components, including transistors and memory, on the back end of a chip without damaging the delicate structures underneath. This innovation opens the door to three-dimensional stacking of active layers that traditionally could not be added because high fabrication temperatures would destroy existing circuits.
A key enabler of the new process is the use of novel material layers that can be grown at low temperatures, such as ultrathin amorphous indium oxide, which functions as a transistor channel without requiring harsh conditions. That makes it possible to build energy-efficient active layers after the main chip is complete. Researchers have also demonstrated back-end transistors with built-in memory using materials such as ferroelectric hafnium-zirconium oxide, boosting integration density while keeping power consumption low.
By shortening the distance data must travel and integrating memory closer to computation, this stacked architecture reduces energy waste and increases processing speed, particularly for demanding applications such as artificial intelligence, deep learning, and other data-intensive tasks. The approach could help address growing electricity use in data centers, mobile devices, and edge computing.
This work, presented at a major electronics conference, points toward a future of more compact, faster, and greener chips by combining innovative materials science with novel manufacturing techniques that rethink the traditional 2D chip design.