The semiconductor industry’s next decade may depend less on shrinking transistors and more on reinventing its structure entirely. According to a new roadmap presented by Belgian research organization Imec, the future of chip manufacturing will move toward vertically stacked transistor designs, atomic-scale semiconductor materials, and deeply integrated three-dimensional computing architectures, tells IEEE Spectrum.
The roadmap predicts that complementary field-effect transistors, or CFETs, will begin entering commercial production around 2033. Unlike today’s CMOS chips, where PMOS and NMOS transistors sit side by side, CFETs stack them vertically to reduce circuit area and improve density. The approach could effectively double transistor packing efficiency while continuing the progress historically associated with Moore’s Law.
Imec believes CFETs will become the semiconductor industry’s next major architectural shift after FinFETs and nanosheet transistors. Major manufacturers, including Intel, Samsung Electronics, and TSMC, are already developing prototype CFET devices. However, researchers acknowledge that the manufacturing process remains highly complex, with multiple competing approaches still under evaluation.
Beyond 2033, the roadmap anticipates another transition around 2041, when silicon transistor channels may begin giving way to two-dimensional semiconductor materials such as molybdenum disulfide. These atomically thin materials could significantly improve power efficiency because their reduced thickness allows lower operating voltages and better electrostatic control.
The article also highlights the growing importance of advanced packaging and 3D chip integration. Rather than treating chips as isolated components, the industry is increasingly stacking multiple dies together using dense interconnect technologies. Imec describes this evolution as “CMOS 2.0,” where chips become fused systems combining specialized layers optimized for different tasks such as memory, logic, and communications.
According to Imec CTO Paul Heremans, the roadmap’s purpose is to “de-risk” future technologies long before commercial deployment becomes possible. That planning reflects the enormous complexity of semiconductor development, where research decisions made today may not influence production systems for another decade or more.