As the Large Hadron Collider (LHC) transitions into its High Luminosity phase (HL-LHC), it’s poised to generate an unprecedented increase in collision rates—from about 400 million to 1.5 billion particle collisions per second. Managing this deluge of data places immense demands on computing systems, including real-time data filtering and high-fidelity signal processing.
IEEE Spectrum reports that to meet these challenges, engineers led by Peter Kinget at Columbia University, in collaboration with the University of Texas at Austin, have developed radiation-hardened analog-to-digital converter (ADC) chips specifically for the ATLAS detector. These chips are engineered to withstand one of the most extreme operational environments imaginable—exposure to radiation levels comparable to eight years in high Earth orbit—without compromising on data integrity.
The ADCs play a pivotal role in the trigger system, swiftly distinguishing meaningful collision events from background noise among vast volumes of raw input—on the order of 60 petabytes of data—by digitizing signals and orchestrating their passage to downstream processing.
A critical innovation in the newer ADC design is the inclusion of a triple-redundancy checking mechanism. This fault-tolerant feature significantly mitigates the risk of data corruption—even in the face of high radiation—by requiring errors to occur in three attempts simultaneously before corrupting data.
These chips are slated for integration during the next LHC shutdown starting in 2026—a once-per-decade hardware refresh that’s essential for fully leveraging the HL-LHC’s upgraded collision capabilities.
These new radiation-resistant ADC chips—and the robust computing architecture they enable—are fundamental to ensuring that engineers and physicists can capture and analyze the staggering volume of high-energy collision data produced by the upgraded LHC.