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S2C, MachineWare, Andes Add Co-emulation for RISC-V Design

by | Dec 16, 2025

A co-emulation solution integrates virtual platforms with FPGA prototyping to support RISC-V chip verification, enabling hardware and software validation in parallel during pre-silicon development and system testing
Image: Andes Technology

SAN JOSE, CA, Dec 16, 2025 – S2C, MachineWare, and Andes Technology have announced a co-emulation solution for RISC-V chip design. The solution links MachineWare’s SIM-V virtual platform with S2C’s FPGA prototyping systems and an Andes AX46MPV RISC-V CPU core for hardware and software co-verification.

RISC-V designs use high-performance, multi-core, and custom architectures, complicating pre-silicon software development and system validation. The co-emulation solution supports a “shift-left” verification approach by moving testing earlier in the design cycle. This allows hardware and software teams to work in parallel, reducing development time and project risk.

MachineWare’s SIM-V: A High-Performance Virtual Platform

MachineWare contributes the SIM-V full-system virtual platform, built on SystemC TLM-2.0, for system-level simulation. The platform supports high simulation speed and connects with third-party toolchains for debugging, testing, and coverage analysis.

SIM-V provides instruction-accurate models for Andes RISC-V processor cores, focusing on simulation performance and system-level validation. The platform implements the AndeStar V5 instruction set architecture, including the RISC-V vector (V) extension. Engineers use the SIM-V extension API to model and test custom processor features. System-level debugging tools provide trace and introspection for detailed analysis.

“Our customers need tools that accelerate development without compromising accuracy,” said Lukas Jünger, CEO of MachineWare. “This co‑emulation solution gives them the ability to validate hardware and software in parallel, reduce integration risks, and bring products to market faster than ever before.”

Andes: High-Performance, Customizable RISC-V Cores

Andes Technology provides CPU IP, including the AndesCore AX46MPV multicore processor. AX46MPV is a 64-bit RISC-V CPU with an 8-stage superscalar pipeline. The design supports up to 16 processor cores and a multi-level cache structure. It includes a Vector Processing Unit (VPU) that supports vector lengths (VLEN) up to 1,024 bits. The processor also supports High-Bandwidth Vector Memory (HVM), and ISA customizations via Andes Custom Extension (ACE).

AX46MPV includes a MMU that supports Linux operating systems. The design supports performance scaling across multiple cores. These features allow use in data center AI compute systems and Linux-based edge AI platforms. The processor also fits high-performance MPUs for storage, networking, and other compute-intensive applications.

“Our customers value our RISC-V IP for its performance, robustness, and ability to add custom extensions that accelerate their key applications.” said Dr. Charlie Su, president and CTO of Andes Technology. “By collaborating with MachineWare and S2C on this co-emulation approach, we’re giving them the ability to evaluate that impact and co-optimize their software stack and silicon architecture before committing to costly silicon tapeout.”

S2C: Bridging Virtual and Physical with Hybrid Emulation

S2C connects the SIM-V virtual platform to hardware using its Genesis Architect and Prodigy FPGA prototyping systems. In this setup, CPU models run in SIM-V while peripheral subsystems run on FPGA hardware. The systems connect through a high-speed transactional bridge for data exchange. This configuration supports execution of software stacks, from bootloader through applications. It also maintains detailed debug visibility during system-level testing and validation.

Key Use Cases & Customer Benefits

The joint solution supports multiple development stages:

  • Pre-silicon software development
  • Hardware/software co-verification
  • System performance analysis and tuning
  • Custom ISA extension development and debug

“Through co-emulation, our customers can accelerate time-to-market, reduce costs, and ensure software maturity – while benefiting from both cycle-accurate debugging and high-speed execution,” said Ying, VP of S2C. “But we can’t achieve this alone. We will continue to build on the high-performance advantages of hardware-assisted verification and work closely with our partners to collaboratively deliver shift-left solutions across the ecosystem.”

Looking Ahead

S2C, MachineWare, and Andes continue to work on verification methods and development tools for RISC-V chip design. Their efforts focus on strengthening the ecosystem for future RISC-V platforms.

Source: Andes Technology

About MachineWare

MachineWare GmbH is a simulation software company founded in 2022 and headquartered in Aachen, Germany. The company develops system-level virtual prototyping tools used for pre-silicon software validation and testing. Its products include virtual platforms, fast simulation models, and QEMU-based tools for software development and verification. MachineWare offers the SIM-V platform for RISC-V system simulation, supporting modeling of complex SoC designs and custom instruction set extensions. The company serves customers in semiconductor design, embedded systems, automotive, AI, telecommunications, and IoT development. Its tools support processor architectures including RISC-V and Arm and focus on early software bring-up and hardware exploration before silicon availability. MachineWare also provides services for simulation enablement and custom model development. MachineWare operates primarily in Europe and supports customers in the Americas and Asia through sales channels and technical partners.

About Andes Technology

Andes Technology is a supplier of high-performance, low-power 32- and 64-bit RISC-V CPU cores and related solutions for embedded systems. Founded in 2005, the company develops configurable processor IP cores used in applications such as AI, 5G communications, Internet of Things (IoT), storage, automotive electronics, and industrial control. Its portfolio includes RISC-V-based CPU cores, development tools, and software designed for energy-efficient, performance-optimized processors. Andes serves industries including consumer electronics, automotive, telecommunications, and industrial automation. Headquartered in Hsinchu Science Park, Taiwan, the company operates globally with a growing presence in Asia, North America, and Europe. Its customer base spans multiple regions, with Taiwan and the United States as key markets. The company continues to invest in R&D to advance processor technologies.

About S2C

S2C is a CA based provider of FPGA prototyping hardware, software, and services used for ASIC and system-on-chip verification. Founded in 2003, the company supports semiconductor, automotive, communications, cloud computing, and IoT customers worldwide. S2C reports more than 600 global customers and about 4,000 system installations. The company employs approx. 126 people. S2C focuses on rapid SoC prototyping to support design verification and development workflows. Its customer base includes semiconductor companies. S2C operates offices and sales locations in San Jose, Seoul, Tokyo, Shanghai, Hsinchu, India, Europe, and the Australia–New Zealand region.